SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 147

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Bus Interface Unit
•
Memory coherency on page 6-9.
Single-layer AHB systems
If the ARM926EJ-S processor is to be used in a single-layer AHB system, each of the
two BIU masters must be treated as being unique.
The simplest way of integrating the two ARM926EJ-S bus masters into a single-layer
AHB system is for each master to be a separate requestor into the AHB arbiter, the same
as for any multi-master system. The data master normally has higher arbitration priority
than the instruction master.
Note
The ARM926EJ-S instruction AHB interface does not perform locked transfers so
IHLOCK is always driven LOW.
DHCLKEN and IHCLKEN must be tied together, as described in AHB clocking on
page 6-10. If HCLK and CLK are the same frequency, DHCLKEN and IHCLKEN
must be tied HIGH.
Because of the handover cycle when transferring ownership of the bus, a nongranted bus
master incurs an extra cycle of latency to get onto the bus if the bus is currently idle.
This means that if the data BIU is the default bus master, it can start AHB transactions
a cycle earlier than the instruction BIU (nondefault bus master), which must wait for
ownership of the bus to be handed over.
This cycle of latency only exists for the first transaction. If the instruction BIU is
prefetching instructions, for example, it can perform back-to-back requests and
maintain ownership of the bus until a higher priority bus master is granted.
Multi-layer AHB systems
Figure 6-1 on page 6-8 shows an example of a Multi-layer AHB system. In this example
the I-interface labeled I-side, and the D-interface labeled D-side are configured through
an interconnect matrix to have access to four slave ports. If the two AHB interfaces,
known as layers, require access to the same slave at the same time, then an arbitration
process within the interconnect matrix determines the layer that has the highest priority.
Under this system D-side can have access to any slave port that I-side is not using at that
time, which increases the overall bus bandwidth available.
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
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