SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 93

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.6
3.6.1
ARM DDI0198D
External aborts
Enabling the MMU
In addition to the MMU generated aborts, external aborts can be generated for certain
types of access that involve transfers over the AHB bus. These can be used to flag errors
on external memory accesses. However, not all accesses can be aborted in this way.
The following accesses can be externally aborted:
•
•
•
•
For a read-lock-write (SWP) sequence, if the read externally aborts, the write is always
attempted.
A swap to an NCB region is forced to have precisely the same behavior as a swap to an
NCNB region. This means that the write part of a swap to an NCB region can be
externally aborted.
Before enabling the MMU using CP15 c1 you must:
1.
2.
When these steps have been performed, you can enable the MMU by setting CP15 c1
bit 0 HIGH.
Care must be taken if the translated address differs from the untranslated address
because several instructions following the enabling of the MMU might have been
prefetched with the MMU off (VA = MVA = PA).
In this case, enabling the MMU can be considered as a branch with delayed execution.
A similar situation occurs when the MMU is disabled. Consider the following code
sequence:
Copyright © 2001-2003 ARM Limited. All rights reserved.
page walks
noncached reads
nonbuffered writes
noncached read-lock-write (SWP) sequence.
Program the TTB register (CP15 c2) and the domain access control register (Cp15
c3).
Program first-level and second-level page tables as required, ensuring that a valid
translation table is placed in memory at the location specified by the TTB register.
Memory Management Unit
3-29