SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 240

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Glossary
Scan chain
SCREG
Set
Set-associative cache
Short vector operation
Should Be One (SBO)
Should Be Zero (SBZ)
Should Be Zero or Preserved (SBZP)
SPICE
SPSR
Tag
Glossary-16
A scan chain is made up of serially-connected devices that implement boundary scan
technology using a standard JTAG TAP interface. Each device contains at least one TAP
controller containing shift registers that form the chain connected between TDI and
TDO, through which test data is shifted. Processors can contain several shift registers
to enable you to access selected parts of the device.
The currently selected scan chain number in an ARM TAP controller.
See Cache set.
In a set-associative cache, lines can only be placed in the cache in locations that
correspond to the modulo division of the memory address by the number of sets. If there
are n ways in a cache, the cache is termed n-way set-associative. The set-associativity
can be any number greater than or equal to 1 and is not restricted to being a power of
two.
An operation involving more than one destination register and perhaps more than one
source register in the generation of the result for each destination.
Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 produces
Unpredictable results.
Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 produces
Unpredictable results.
Should be written as 0 (or all 0s for bit fields) by software, or preserved by writing the
same value back that has been previously read from the same field on the same
processor.
Simulation Program with Integrated Circuit Emphasis. An accurate transistor-level
electronic circuit simulation tool that can be used to predict how an equivalent real
circuit will behave for given circuit conditions.
See Saved Program Status Register
The upper portion of a block address used to identify a cache line within a cache. The
block address from the CPU is compared with each tag in a set in parallel to determine
if the corresponding line is in the cache. If it is, it is said to be a cache hit and the line
can be fetched from cache. If the block address does not correspond to any of the tags,
it is said to be a cache miss and the line must be fetched from the next level of memory.
See also Cache terminology diagram on the last page of this glossary.
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