SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 37

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
31 30 29 28
0
0 0
Ctype
S bit
Dsize
Isize
The Ctype field specifies if the cache supports lockdown or not, and how it is cleaned.
The encoding is shown in Table 2-6. All unused values are reserved.
The Dsize and Isize fields in the Cache Type Register have the same format. This is
shown in Figure 2-3.
Size
Ctype
Copyright © 2001-2003 ARM Limited. All rights reserved.
25 24 23
S
The Ctype field determines the cache type. See Table 2-6.
Specifies if the cache is a unified cache (S=0), or separate ICache and
DCache (S=1). If S=0, the Isize and Dsize fields both describe the unified
cache and must be identical. In the ARM926EJ-S processor, this bit is set
to a 1 to denote separate caches.
Specifies the size, line length, and associativity of the DCache, or of the
unified cache if the S bit is 0.
Specifies the size, length, and associativity of the ICache, or of the
unified cache if the S bit is 0.
The Size field determines the cache size in conjunction with the M bit.
Value
b1110
a. See Cache Lockdown Register c9 on page 2-26 for more details on
Format C for cache lockdown.
Method
Write-back
Dsize
Cache cleaning
Register 7 operations
Figure 2-2 Cache Type Register format
Figure 2-3 Dsize and Isize field format
12 11
11 10 9
0 0
Table 2-6 Ctype encoding
Size
Isize
6 5
Format C
Cache lockdown
Programmer’s Model
Assoc M Len
3 2 1 0
a
0
2-9