DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1019

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SIV53002-4.1
Stratix IV Device Handbook Volume 3
February 2011
February 2011
SIV53002-4.1
This chapter describes the Altera-recommended basic design flow that simplifies
Stratix
Use the following design flow techniques to simplify transceiver implementation. The
“Guidelines to Debug Transceiver-Based Designs” on page 2–14
to trouble-shoot transceiver-based designs. An example of a fibre channel protocol
application is also described in this chapter.
The transceiver-based design is divided into phases and are detailed in the following
sections:
■
■
■
■
■
■
Figure 2–1
design flow stages include architecture, functional simulation, compilation, and
verification. Each stage of the design flow is explained in the sections that follow.
“Architecture” on page 2–3
“Implementation and Integration” on page 2–6
“Compilation” on page 2–10
“Verification” on page 2–12
“Functional Simulation” on page 2–12
“Example 1: Fibre Channel Protocol Application” on page 2–17
®
IV GX transceiver-based designs.
shows the design flow chart of the different stages of the design flow. The
2. Transceiver Design Flow Guide for
Stratix IV Devices
provides guidelines
Subscribe