DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 736

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

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Stratix IV Device Handbook Volume 2: Transceivers
1
Non-Bonded Channel Configuration Without Rate Matcher
In non-bonded channel configuration without rate matcher, the Quartus II software
cannot determine if the incoming serial data in all channels have a 0 PPM frequency
difference. The Quartus II software automatically drives the read port of the receiver
phase compensation FIFO in each channel with the recovered clock driven on the
rx_clkout port of that channel. Use the rx_clkout signal from each channel to latch
its receiver data and status signals in the FPGA fabric.
This configuration uses one FPGA global, regional clock, or both, resource per
channel for the rx_clkout signal.
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation