DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 925

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 4 of 13)
February 2011 Altera Corporation
busy
read
data_valid
error
Port Name
Output
Output
Output
Output
Input/
Input
This signal is used to indicate the busy status of the dynamic
reconfiguration controller during offset cancellation. After the
device powers up, this signal remains low for the first
reconfig_clk clock cycle. It then is asserted and remains high
when the dynamic reconfiguration controller performs offset
cancellation on all the receiver channels connected to the
ALTGX_RECONFIG instance.
De-assertion of the
completion of the offset cancellation process.
For more information, refer to
■
■
Assert this signal for one reconfig_clk clock cycle to initiate a
read transaction. The read port is applicable only to the PMA
controls reconfiguration mode and data rate division in transmitter
mode. The read port is available when you select Analog controls
in the Reconfiguration settings screen and select at least one of
the PMA control ports in the Analog controls screen.
For more information, refer to
Controls” on page
Applicable only to PMA controls reconfiguration mode. This port
indicates the validity of the data read from the transceiver by the
dynamic reconfiguration controller.
The current data on the output read ports is the valid data ONLY if
data_valid is high.
This signal is enabled when you enable at least one PMA control
port used in read transactions, for example tx_vodctrl_out.
This indicates that an unsupported operation is attempted. You can
select this in the Error checks/Data rate switch screen. The
dynamic reconfiguration controller de-asserts the busy signal and
asserts the error signal for two reconfig_clk cycles when you
attempt an unsupported operation.
For more information, refer to the
Reconfiguration” on page
PMA controls reconfiguration mode—This signal is high when
the dynamic reconfiguration controller performs a read or write
transaction.
All other dynamic reconfiguration modes—This signal is high
when the dynamic reconfiguration controller writes the .mif into
the transceiver channel.
5–13.
busy signal indicates the successful
Stratix IV Device Handbook Volume 2: Transceivers
5–88.
Description
“Operation” on page
“Dynamically Reconfiguring PMA
“Error Indication During Dynamic
(Note
5–66.
3),
(4)
5–79