DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 697

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–15. Transmitter Datapath Clocking in a Non-Bonded Configuration Clocked by CMU PLLs
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, and the blue lines
February 2011 Altera Corporation
tx_coreclk[3]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[0]
represent the ×1 high-speed serial clock.
Fabric
FPGA
Figure
2–15:
FPGA Fabric-Transceiver
FPGA Fabric-Transciever
FPGA Fabric-Transceiver
FPGA Fabric-Transciever
hard IP
hard IP
Interface Clock
Interface Clock
hard IP
PCIe
hard IP
PCIe
PCIe
Interface Clock
Interface Clock
PCIe
Figure 2–15
configurations when clocked using the CMU PLLs.
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
Reference
Reference
PIPE
Clock
Input
Clock
Input
tx_clkout[3]
tx_clkout[1]
tx_clkout[2]
tx_clkout[0]
shows transmitter channel datapath clocking in non-bonded channel
CMU1 PLL
CMU0 PLL
Compensation
Compensation
wrclk
wrclk
wrclk
wrclk
Compensation
Compensation
TX Phase
TX Phase
TX Phase
TX Phase
FIFO
FIFO
FIFO
FIFO
rdclk
rdclk
rdclk
rdclk
Divider
Divider
CMU1
CMU0
Clock
Clock
wrclk
wrclk
wrclk
wrclk
Serializer
Serializer
Serializer
Serializer
Byte
Byte
Byte
Byte
/
/
/
/
2
2
2
2
rdclk
rdclk
rdclk
rdclk
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
8B/10B
Encoder
8B/10B
Encoder
8B/10B
Encoder
8B/10B
Encoder
Stratix IV Device Handbook Volume 2: Transceivers
CMU1 Channel
CMU0 Channel
Channel 0
Channel 3
Channel 1
Channel 2
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Serializer
Serializer
Serializer
Serializer
(Note 1)
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
2–25