DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 49

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
February 2011 Altera Corporation
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in
arithmetic or shared-arithmetic mode. The two-bit carry select feature in Stratix IV
devices halves the propagation delay of carry chains within the ALM. Carry chains
can begin in either the first ALM or the fifth ALM in the LAB. The final carry-out
signal is routed to the ALM, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry-chain logic during design
processing, or you can create it manually during design entry. Parameterized
functions such as LPM functions automatically take advantage of carry chains for the
appropriate functions.
The Quartus II Compiler creates carry chains longer than 20 (10 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. For enhanced
fitting, a long carry chain runs vertically, allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high fan-in
arithmetic function is implemented, the LAB can support carry chains that only use
either the top half or bottom half of the LAB before connecting to the next LAB. This
leaves the other half of the ALMs in the LAB available for implementing narrower
fan-in functions in normal mode. Carry chains that use the top five ALMs in the first
LAB carry into the top half of the ALMs in the next LAB within the column. Carry
chains that use the bottom five ALMs in the first LAB carry into the bottom half of the
ALMs in the next LAB within the column. In every alternate LAB column, the top half
can be bypassed; in the other MLAB columns, the bottom half can be bypassed.
For more information about carry-chain interconnects, refer to
on page
2–18.
Stratix IV Device Handbook Volume 1
“ALM Interconnects”
2–13