DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1136
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 1136 of 1154
- Download datasheet (32Mb)
1–54
Table 1–41. High-Speed I/O Specifications
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Transmitter
True Differential I/O
Standards - f
(data rate)
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - f
(data rate)
Emulated
Differential I/O
Standards with One
External Output
Resistor - f
(data rate)
t
Differential I/O
Standards
t
Differential I/O
Standards with
Three External
Output Resistor
Network
t
Differential I/O
Standards with One
External Output
Resistor Network
t
t
DUTY
RISE &
x Jitter
x Jitter
x Jitter
Symbol
- True
- Emulated
- Emulated
t
FALL
HSDR
(5)
HSDR
HSDR
SERDES factor J = 3 to 10
True Differential I/O Standards
Standards with Three External
Tx output clock duty cycle for
Standards with One External
SERDES factor J = 4 to 10
Output Resistor Networks
Differential I/O Standards
Total Jitter for Data Rate,
Total Jitter for Data Rate,
Total Jitter for Data Rate,
Emulated Differential I/O
Emulated Differential I/O
Total Jitter for Data Rate
600 Mbps to 1.25 Gbps
both True and Emulated
600 Mbps to 1.6 Gbps
Uses an SDR Register
SERDES factor J = 2,
SERDES factor J = 1,
Uses DDR Registers
Output Resistor
< 600 Mbps
< 600 Mbps
Conditions
—
(Note 1), (2), (10)
(8)
–2/–2× Speed Grade
Min
—
—
—
—
—
45
—
—
—
(4)
(4)
(4)
(4)
(4)
Typ
—
—
—
—
—
—
—
—
—
—
50
—
—
—
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
(Part 2 of 3)—Preliminary
0.125
1600
1250
Max
311
160
300
160
250
460
0.1
0.2
55
(4)
(4)
Min
(4)
(4)
(4)
(4)
(4)
—
—
—
—
—
45
—
—
—
–3
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
50
—
—
—
1250
1152
0.15
Max
200
160
300
200
250
500
0.1
0.2
(4)
(4)
55
April 2011 Altera Corporation
Min
—
—
—
—
—
45
—
—
—
(4)
(4)
(4)
(4)
(4)
Switching Characteristics
–4
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
50
—
—
—
1250
Max
0.25
0.15
800
200
160
325
200
300
500
0.1
55
(4)
(4)
Mbps
Mbps
Mbps
Mbps
Mbps
Unit
ps
UI
ps
UI
UI
ps
ps
ps
%
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