DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 781

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
Example 5
Consider a design example configuration with a Basic (PMA Direct) ×1 instance with
the number of channels set to 7 in the ALTGX MegaWizard Plug-In Manager. With
this setting, the ALTGX MegaWizard Plug-In Manager provides 7 bits of
gxb_powerdown, rx_analogreset, and pll_powerdown ports.
In this case, the Quartus II software attempts to combine the five channels in the
instance to one transceiver block and the remaining two channels to the second
transceiver block, assuming that the gxb_powerdown and pll_powerdown ports for the
five channels are driven from the same logic.
conditions before and after compilation.
Figure 3–12. Logical View of the Instance with Seven Channels Before Compilation for
Example 5
Receiver and Transmitter configuration:
Basic (PMA Direct) x1 mode
Number of channels = 7
Inst0
Figure 3–12
Stratix IV Device Handbook Volume 2: Transceivers
and
CMU PLL
Figure 3–13
show the
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