DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 580

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–136
Table 1–49. Power State Functions and Descriptions
Figure 1–113. Power State Transition from the P0 to P2 Power State
Stratix IV Device Handbook Volume 2: Transceivers
Power State
P0s
P0
P1
P2
pipephydonestatus
1
powerdn[1:0]
powerdn
Parallel
2’b00
2’b01
2’b10
2’b11
Clock
The PCIe specification provides the mapping of these power states to the LTSSM
states specified in the PCIe Base Specification 2.0. The PHY-MAC layer is responsible
for implementing the mapping logic between the LTSSM states and the four power
states in the PCIe-compliant PHY.
The PCIe interface in Stratix IV GX and GT transceivers provides an input port,
powerdn[1:0], for each transceiver channel configured in PCIe mode.
mapping between the logic levels driven on the powerdn[1:0] port and the resulting
power state that the PCIe interface block puts the transceiver channel into.
When transitioning from the P0 power state to lower power states (P0s, P1, and P2),
the PCIe specification requires the physical layer device to implement power saving
measures. Stratix IV GX and GT transceivers do not implement these power saving
measures except putting the transmitter buffer in electrical idle in the lower power
states.
The PCIe interface block indicates successful power state transition by asserting the
pipephydonestatus signal for one parallel clock cycle as specified in the PCIe
specification. The PHY-MAC layer must not request any further power state
transition until the pipephydonestatus signal has indicated the completion of the
current power state transition request.
Figure 1–113
state.
Transmits normal data, transmits electrical idle, or
enters into loopback mode
Only transmits electrical idle
Transmitter buffer is powered down and can do a
receiver detect while in this state
Transmits electrical idle or a beacon to wake up the
downstream receiver
2'b00 (P0)
shows an example waveform for a transition from the P0 to P2 power
Function
2'b11 (P2)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Normal operation mode
Low recovery time saving state
High recovery time power saving
state
Lowest power saving state
February 2011 Altera Corporation
Description
Transceiver Block Architecture
Table 1–49
lists