DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 897

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
ALTGX MegaWizard Plug-In Manager Setup for Channel Reconfiguration with Transmitter PLL
Select Mode
Follow steps 1, 2, 4, 7, 8, and 9 described in
Setup for Channel and CMU PLL Reconfiguration Mode” on page
these steps, you must also set up the following:
The Use additional CMU/ATX Transmitter PLLs from outside the transceiver block
option allows you select a maximum of four transmitter PLLs.
Specify the number of additional PLLs required for the ALTGX instance in the Modes
screen. Based on this number, the Quartus II software opens up the corresponding
PLL screens (for example, PLL 1 and PLL 2).
The PLL set up in the General screen is always the Main PLL and the settings are
available in the Main PLL screen. Similarly, the PLL settings for the additional PLLs
are available in the corresponding PLL1 screen, PLL 2 screen, and so on.
Additional PLLs also include the CMU PLLs within the same transceiver block.
For example, you can select the ATX PLL as the main PLL, and three additional PLLs
as follows:
■
■
■
The Quartus II software differentiates between the CMU PLLs of the same transceiver
block and the transmitter PLLs outside the transceiver block based on the Use central
clock divider to drive the transmitter channels using ×4/×N lines option.
If you enable this option, the transmitter PLL is outside the transceiver block.
Similarly, if you disable option, the transmitter PLL is one of the CMU PLLs within
the same transceiver block.
The logical channel addressing of the transceiver channel is the same as described in
“Logical Channel Addressing” on page 5–5
CMU PLLs within the same transceiver block.
In the case of additional PLLs (when transmitter PLLs are outside the transceiver
block), the additional PLLs also have their own logical channel address. This affects
the starting channel number of the following ALTGX instances connected to the
dynamic reconfiguration controller, if any. Therefore, you must take into account the
logical channel address of transmitter PLLs outside the transceiver block when setting
the Total number of channels controlled by the reconfig controller option in the
ALTGX_RECONFIG instance.
When you select the Use central clock divider to drive the transmitter channels
using ×4/×N lines option for an additional PLL, you can see its logical channel
address value at the bottom of the corresponding PLL screen.
PLL 1—CMU0 PLL of the same transceiver block
PLL 2—CMU1 PLL of the same transceiver block
PLL 3—CMU0 PLL/CMU1 PLL of another transceiver block.
Multi-PLL Settings
Logical Channel Addressing When Using Additional PLLs
“ALTGX MegaWizard Plug-In Manager
so long as you are ONLY using the
Stratix IV Device Handbook Volume 2: Transceivers
5–26. In addition to
5–51