DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 86
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 86 of 1154
- Download datasheet (32Mb)
4–6
Figure 4–4. Output Cascading Feature for FIR Structures
Stratix IV Device Handbook Volume 1
Input
Data
Half DSP Block
144
To support commonly found FIR-like structures efficiently, a major addition to the
DSP block in Stratix IV devices is the ability to propagate the result of one half block
to the next half block completely within the DSP block without additional soft logic
overhead. This is achieved by the inclusion of a dedicated addition unit and routing
that adds the 44-bit result of a previous half block with the 44-bit result of the current
block. The 44-bit result is either fed to the next half block or out of the DSP block using
the output register stage, as shown in
later sections.
The combination of a fast, low-latency four-multiplier adder unit and the “chained
cascade” capability of the output chaining adder provides the optimal FIR and vector
multiplication capability.
To support single-channel type FIR filters efficiently, you can configure one of the
multiplier input’s registers to form a tap delay line input, saving resources and
providing higher system performance.
Also shown in
unit provides a rich set of commonly found arithmetic rounding and saturation
functions used in signal processing.
In addition to the independent multipliers and sum modes, you can use DSP blocks to
perform shift operations. DSP blocks can dynamically switch between logical shift
left/right, arithmetic shift left/right, and rotation operation in one clock cycle.
Figure 4–4
is the optional rounding and saturation unit (RSU). This
From Previous Half DSP Block
Figure
4–4. Detailed examples are described in
To Next
Half DSP Block
44
44
Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
February 2011 Altera Corporation
Result[]
44
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