DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 502
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 502 of 1154
- Download datasheet (32Mb)
1–58
Figure 1–47. Deserializer Operation in Single-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
f
After offset cancellation is complete, the divider settings are restored. Then the
reconfiguration block sends and receives data to the ALTGX instance using the
reconfig_togxb and reconfig_fromgxb buses. Connect the buses between the
ALTGX_RECONFIG and ALTGX instances. The de-assertion of the busy signal from
the offset cancellation control logic indicates the offset cancellation process is
complete.
Due to the offset cancellation process, the transceiver reset sequence has changed. For
more information about the offset cancellation process, refer to the
Power Down in Stratix IV Devices
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes it using the low-speed parallel
recovered clock. It forwards the deserialized data to the receiver PCS channel.
In single-width mode, the deserializer supports 8-bit and 10-bit deserialization
factors. In double-width mode, the deserializer supports 16-bit and 20-bit
deserialization factors.
Figure 1–47
deserialization factor.
Received Data
Recovery
Clock
Unit
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock
shows the deserializer operation in single-width mode with a 10-bit
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
chapter.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Chapter 1: Transceiver Architecture in Stratix IV Devices
10
To Word
Aligner
February 2011 Altera Corporation
Transceiver Block Architecture
Reset Control and
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