DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 685

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
Figure 2–8. FPGA Fabric PLLs-Transceiver PLLs Cascading Options Allowed in the 1932-Pin Package Device
February 2011 Altera Corporation
FPGA Fabric PLLs-Transceiver PLLs Cascading in the 1932-Pin Package
Transceiver Block GXBL2
Channel 2
Channel 3
Transceiver Block GXBL0
Channel 3
Channel 2
Channel 2
Transceiver Block GXBL1
Channel 3
Channel 1
Channel 0
Channel 1
Channel 0
Transceiver Block GXBL3
Channel 3
Channel 1
Channel 0
Channel 1
Channel 0
Channel 2
ATX PLL L1 (6G)
ATX PLL L0 (6G)
1
CMU1
CMU0
CMU1
CMU0
CDR
CMU1
CMU0
CMU1
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Figure 2–8
in the EP4SGX530NF45, EP4SGX360NF45, and EP4SGX290NF45 devices.
For Stratix IV GT devices, FPGA fabric PLLs-Transceiver PLLs cascading is not
supported for the 10G ATX PLLs. For the EP4S100G3NF45, EP4S100G4N45, and
EP4S100G5NF45 devices, FPGA fabric PLLs-Transceiver PLLs cascading for the
6G ATX PLLs and CMU PLLs is the same as the Stratix IV GX devices in the 1932-pin
package.
Cascade
Network
PLL
shows the FPGA fabric PLLs-Transceiver PLLs cascading options allowed
PLL_L4
PLL_L1
PLL_L2
PLL_L3
EP4SGX530NF45
EP4SGX360NF45
EP4SGX290NF45
PLL_R2
PLL_R3
PLL_R1
PLL_R4
Stratix IV Device Handbook Volume 2: Transceivers
Cascade
Network
PLL
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR1
ATX PLL R0 (6G)
ATX PLL R1 (6G)
CMU1
CMU1
CMU1
CMU0
CMU0
CMU1
CMU0
CDR
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
Channel 1
Channel 3
Channel 3
Channel 2
Channel 1
Channel 3
Channel 2
Channel 0
Channel 3
Channel 2
Channel 0
Channel 2
Channel 1
Channel 1
Channel 0
Channel 0
2–13