DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 517
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 517 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
By default, the Stratix IV GX and GT receiver assumes a LSB-to-MSB transmission. If
the transmission order is MSB-to-LSB, the receiver forwards the bit-flipped version of
the parallel data to the FPGA fabric on the rx_dataout port. The receiver bit reversal
feature is available to correct this situation.
The receiver bit reversal feature is available through the rx_revbitordwa port only in
Basic single-width and double-width modes with the word aligner configured in
bit-slip mode. When the rx_revbitordwa signal is driven high in Basic single-width
mode, the 8-bit or 10-bit data D[7:0] or D[9:0] at the output of the word aligner gets
rewired to D[0:7] or D[0:9], respectively. When the rx_revbitordwa signal is driven
high in Basic double-width mode, the 16-bit or 20-bit data D[15:0] or D[19:0] at the
output of the word aligner gets rewired to D[0:15] or D[0:19], respectively.
Flipping the parallel data using this feature allows the receiver to forward the correct
bit-ordered data to the FPGA fabric on the rx_dataout port in the case of MSB-to-LSB
transmission.
Figure 1–55
datapath configurations.
Figure 1–55. Receiver Bit Reversal in Single-Width Mode
Receiver Bit Reversal
shows the receiver bit reversal feature in Basic single-width 10-bit wide
Output of Word Aligner before
RX bit reversal
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
rx_revbitordwa = high
Output of Word Aligner after RX
Stratix IV Device Handbook Volume 2: Transceivers
bit reversal
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
1–73
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