DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 790

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–36
Stratix IV Device Handbook Volume 2: Transceivers
You can place channels within a given instance non-contiguously, as shown in
Figure
Figure 3–19. Non-Contiguous Placements of Channels Using Different CMU PLLs for Example 8
Note to
(1) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black lines represent
the ×N bottom clock line.
Figure
3–19.
3–19:
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Base data rate
Base data rate
CMU0 PLL
CMU0 PLL
1.25 Gbps
1.5 Gbps
RX
RX
RX
RX
RX
RX
Transceiver Block 2
CMU0 Channel
Inst1: Channel 0
Inst1: Channel 1
CMU0 Channel
RX
RX
RX
RX
RX
Inst1: Channel 2
Inst0: Channel 5
Inst1: Channel 3
Inst1: Channel 4
Inst0: Channel 1
Inst0: Channel 2
Inst0: Channel 0
Inst0: Channel 4
Inst0: Channel 3
GXBR1
GXBR0
Combining Transceiver Channels in Basic (PMA Direct) Configurations
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
Central
Divider
Clock
Central
Divider
Clock
xN Bottom Clock Line (1)
x4 Clock Line (1)
xN Top Clock Line (1)
February 2011 Altera Corporation