DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 215

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–31. LVDS I/O Standard Termination
Notes to
(1)
(2) Side I/O banks support true LVDS output buffers.
(3) Column and side I/O banks support LVDS_E_1R and LVDS_E_3R I/O standards using two single-ended output buffers.
February 2011 Altera Corporation
For LVDS output with a three-resistor network, the R
R
P
value is 120
Figure
with Three-Resistor
External On-Board
with One-Resistor
6–31:
OCT Receive
(Single-Ended
(Single-Ended
OCT Receive
LVDS_E_1R)
OCT Receive
LVDS_E_3R)
LVDS Output
LVDS Output
Termination
(True LVDS
Termination
Network,
Network,
Ω.
Output)
(2)
(3)
(3)
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O interface standard. In Stratix IV devices, the LVDS I/O standard
requires a 2.5-V V
standard in applications requiring high-bandwidth data transfer, such as backplane
drivers and clock distribution. LVDS requires a 100-Ω termination resistor between the
two signals at the input buffer. Stratix IV devices provide an optional 100-Ω
differential termination resistor in the device using on-chip differential termination.
Figure 6–31
available in the row I/O banks.
Differential Outputs
Differential Outputs
Single-Ended Outputs
Single-Ended Outputs
shows LVDS termination. The on-chip differential resistor is only
CCIO
S
and R
(Note 1)
level. The LVDS input buffer requires 2.5-V V
P
values are 120 and 170
External Resistor
≤ 1 inch
≤ 1 inch
External Resistor
Rs
Rs
Rp
Rp
LVDS
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Ω , respectively. For LVDS output with a one-resistor network, the
100 Ω
100 Ω
100 Ω
100 Ω
Stratix IV Device Handbook Volume 1
Stratix IV OCT
Differential Inputs
Differential Inputs
Differential Inputs
Stratix IV OCT
Stratix IV OCT
Differential Inputs
CCPD
. Use this
6–43