DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 849

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Architecture
Dynamic Reconfiguration Controller Architecture
Figure 5–1. Dynamic Reconfiguration Controller
Notes to
(1) The PMA control ports consist of the V
(2) For more information, refer to
February 2011 Altera Corporation
rate_switch_ctrl[1:0](TX only)
logical_channel_address[]
rx_tx_duplex_sel[]
reconfig_reset
reset_reconfig_address
reconfig_data[15:0]
logical_tx_pll_sel_en
logical_tx_pll_sel
PMA control ports (1)
reconfig_address[5:0] (2)
ctrl_write
ctrl_read
ctrl_address[15:0]
ctrl_writedata[15:0]
Figure
reconfig_clk
read
write_all
5–1:
1
The dynamic reconfiguration controller is a soft IP that utilizes FPGA-fabric
resources. You can use only one controller per transceiver block. You cannot use the
dynamic reconfiguration controller to control multiple Stratix IV devices or any
off-chip interfaces.
reconfiguration controller architecture. For a detailed description of the inputs and
outputs of the ALTGX_RECONFIG instance, refer to
Controller Port List” on page
You can use only one ALTGX_RECONFIG instance per transceiver block. You may
use a single ALTGX_RECONFIG instance with multiple transceiver blocks.
reconfig_mode_sel[]
Table 5–16 on page
ALTGX_RECONFIG MegaWizard Plug-In Manager
PMA controls
reconfig logic
control logic
control logic
control logic
control logic
control logic
Cancellation
control logic
reconfig with
control logic
Control Unit
Data Rate
CMU PLL
CMU PLL
Reconfig
Channel
Channel
reconfig
Central
reconfig
TX PLL
select
Switch
EyeQ
logic
Offset
AEQ
and
OD
, pre-emphasis, DC gain, and manual equalization controls.
(Dynamic Reconfiguration Controller)
ALTGX_RECONFIG Instance
Figure 5–1
5–76.
Translation
Address
5–76.
shows a conceptual view of the dynamic
addr
data
Converter
Parallel
Serial
to
Stratix IV Device Handbook Volume 2: Transceivers
“Dynamic Reconfiguration
rate_switch_out_[1:0]
(TX only)
reconfig_fromgxb[]
reconfig_togxb[3:0]
data valid
busy
error
ctrl_readdata[15:0]
ctrl_waitrequest
reconfig_address_out[6:0]
reconfig_address_en
channel_reconfig_done
aeq_togxb[]
aeq_fromgxb[]
ALTGX MegaWizard
Plug-In Manager
ALTGX Instances
5–3