DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 707
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 707 of 1154
- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–21. Transmitter Channel PMA Directly Interfacing to the User Logic in the FPGA Fabric
Note to
(1) The green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock.
February 2011 Altera Corporation
Figure
2–21:
1
FPGA
Fabric
Stratix IV devices do not allow the 6G ATX PLL to generate transceiver clocks in
non-bonded Basic (PMA Direct) mode. The transmitter clock for channels configured
in non-bonded Basic (PMA Direct) mode must be generated by one of the CMU PLLs
in the transceiver block containing the channels.
tx_clkout[3]
tx_clkout[2]
tx_clkout[1]
tx_clkout[0]
CMU0_PLL
Divider
CMU1
Divider
CMU0
Clock
Clock
CMU1_Channel
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Low-Speed Parallel Clock
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU0_Channel
Channel 1
Channel 0
Channel 3
Channel 2
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Serializer
Serializer
Serializer
Serializer
Serializer
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
x1 High-Speed Serial Clock
(Note 1)
2–35
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