DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 419

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SIV51012-3.2
BST Architecture
Stratix IV Device Handbook Volume 1
February 2011
February 2011
SIV51012-3.2
f
The IEEE Std. 1149.1 boundary-scan test (BST) circuitry available in Stratix
devices provides a cost-effective and efficient way to test systems that contain devices
with tight lead spacing. Circuit boards with Altera and other IEEE Std.
1149.1-compliant devices can use EXTEST, SAMPLE/PRELOAD, and BYPASS modes to
create serial patterns that internally test the pin connections between devices and
check device operation.
This chapter describes how to use the IEEE Std. 1149.1 BST circuitry in Stratix IV
devices. The features are similar to Stratix III devices, unless stated otherwise in this
chapter.
This chapter contains the following sections:
■
■
■
■
■
A device operating in IEEE Std. 1149.1 BST mode uses four required pins, TDI, TDO,
TMS, TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down
resistor, while the TDI, TMS, and TRST pins have internal weak pull-up resistors. The
TDO output pin and all the JTAG input pins are powered by the 2.5-V/3.0-V V
supply of I/O bank 1A. All user I/O pins are tri-stated during JTAG configuration.
For more information about the description and functionality of all JTAG pins,
registers used by the IEEE Std. 1149.1 BST circuitry, and the test access port (TAP)
controller, refer to the
chapter in volume 1 of the Stratix III Device Handbook.
“BST Architecture”
“BST Operation Control” on page 12–2
“I/O Voltage Support in a JTAG Chain” on page 12–4
“BST Circuitry” on page 12–4
“BSDL Support” on page 12–4
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
12. JTAG Boundary-Scan Testing in
Stratix IV Devices
®
IV
CCPD
Subscribe