DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 305

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
Table 8–10. Signal Interface Between ALTPLL and ALTLVDS Megafunctions (Part 2 of 2)
Figure 8–21. LVDS Interface with the ALTPLL Megafunction
Note to
(1) Instantiation of pll_areset is optional for the ALTPLL instantiation.
February 2011 Altera Corporation
Parallel clock output (c2)
~(locked)
Notes to
(1) The serial clock output (c0) can only drive tx_inclock on the ALTLVDS transmitter and rx_inclock on the ALTLVDS receiver. This clock
(2) The pll_areset signal is automatically enabled for the LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter
cannot drive the core logic.
instantiation when the external PLL option is enabled.
Figure
From the ALTPLL
Table
Megafunction
8–21:
8–10:
1
The rx_syncclock port is automatically enabled in an LVDS receiver in external PLL
mode. The Quartus II compiler errors out if this port is not connected, as shown in
Figure
When generating the ALTPLL megafunction, the Left/Right PLL option is configured
to set up the PLL in LVDS mode.
ALTPLL and ALTLVDS megafunctions.
Transmitter Core Logic
Receiver Core Logic
8–21.
FPGA Fabric
tx_coreclk
rx_coreclk
Parallel clock used inside the transmitter core
logic in the FPGA fabric
To the ALTLVDS Transmitter
tx_in
rx_out
LVDS Transmitter
LVDS Receiver
(ALTLVDS)
(ALTLVDS)
—
rx_syncclock
rx_inclock
pll_areset
tx_inclock
tx_enable
rx_enable
(Note 1)
Figure 8–21
shows the connection between the
c2
locked
c0
c1
rx_syncclock (parallel clock input) and
parallel clock used inside the receiver
core logic in the FPGA fabric
pll_areset (asynchronous PLL reset
port)
ALTPLL
pll_areset
(2)
To the ALTLVDS Receiver
inclk0
Stratix IV Device Handbook Volume 1
8–27