DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 776
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 776 of 1154
- Download datasheet (32Mb)
3–22
Figure 3–10. Basic ×8/PCIe ×8 Functional Mode Configuration when Combining Channels (ATX PLL)
Notes to
(1) You can configure this channel in Basic (PMA Direct) single-width or double-width mode.
(2) You can configure this channel only in Basic (PMA Direct) single-width mode.
(3) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents the ×N bottom clock line.
(4) To simplify the illustration, only the transmitter side is shown. PCIe ×8 refers to PCIe with the sub protocol set to Gen1 ×8 and Gen2 ×8.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
3–10:
[PMA Direct] xN mode) (2)
[PMA Direct] xN mode) (2)
TX - (Basic
TX - (Basic
Master Transceiver Block
Slave Transceiver Block
CMU0 Channel
CMU0 Channel
(Basic [PMA Direct] xN mode) (1)
TX7 - Basic x8/
TX6 - Basic x8/
(PMA Direct xN mode) (1)
TX2 - Basic x8/
TX5 - Basic x8/
TX3 - Basic x8/
TX0 - Basic x8/
TX4 - Basic x8/
TX1 - Basic x8/
ATX PLL
ATX PLL
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
CMU1 Channel
CMU1 Channel
Central Clock
Central Clock
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Divider
Divider
Combining Channels Configured in Protocol Functional Modes
xN Top Clock Line (3)
x4 Clock Line (3)
x4 Clock Line (3)
xN Bottom Clock Line (3)
xN Bottom Clock Line (3)
February 2011 Altera Corporation
(Note 4)
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: