DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 860

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–14
Figure 5–5. Method 1—Write Transaction Waveform
Stratix IV Device Handbook Volume 2: Transceivers
logical_address_channel [1:0]
rx_tx_duplex_sel [1:0]
Figure 5–5
example, the number of channels connected to the dynamic reconfiguration controller
is four. Therefore, the logical_channel_address port is 2 bits wide. Also, to initiate
the write transaction, you must assert the write_all signal for one reconfig_clk
cycle.
tx_vodctrl [2:0]
reconfig_clk
Write Transaction
write_all
busy
shows the write transaction waveform when using Method 1. In this
2’b00
2’b00
3’b00
2’b01 (second channel of the ALTGX instance)
2’b10 (transmitter portion only)
3’b11
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation