DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 41

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Adaptive Logic Modules
Figure 2–4. LAB-Wide Control Signals
Adaptive Logic Modules
February 2011 Altera Corporation
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control
signals. The MultiTrack interconnect’s inherent low skew allows clock and control
signal distribution in addition to data.
The ALM is the basic building block of logic in the Stratix IV architecture. It provides
advanced features with efficient logic usage. Each ALM contains a variety of
LUT-based resources that can be divided between two combinational adaptive LUTs
(ALUTs) and two registers. With up to eight inputs for the two combinational ALUTs,
one ALM can implement various combinations of two functions. This adaptability
allows an ALM to be completely backward-compatible with four-input LUT
architectures. One ALM can also implement any function with up to six inputs and
certain seven-input functions.
6
6
6
labclk0
clock signals per LAB.
There are two unique
or asyncload
or labpreset
labclkena0
labclk1
labclkena1
labclk2
labclkena2
syncload
Stratix IV Device Handbook Volume 1
labclr0
labclr1
synclr
2–5