DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 299

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Figure 8–16. Receiver Data Re-alignment Rollover
February 2011 Altera Corporation
rx_channel_data_align
rx_cda_max
rx_outclock
rx_inclock
Figure 8–15
deserialization factor set to 4.
Figure 8–15. Data Realignment Timing
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set equal to or greater than the deserialization factor, allowing enough depth in the
word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the MegaWizard Plug-In Manager software. An optional status
port, RX_CDA_MAX, is available to the FPGA fabric from each channel to indicate when
the preset rollover point is reached.
Figure 8–16
rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has
occurred.
rx_channel_data_align
shows receiver output (RX_OUT) after one bit slip pulse with the
shows a preset value of four bit-times before rollover occurs. The
rx_outclock
rx_inclock
rx_out
rx_in
3
2
3210
1
0
3
2
321x
1
0
3
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1
0
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