DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 523

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–60. Rate Match Deletion in PCIe Mode
Figure 1–61. Rate Match Insertion in PCIe Mode
February 2011 Altera Corporation
pipestatus[2:0]
dataout
pipestatus[2:0]
datain
dataout
datain
3'b001
K28.5
K28.5
First Skip Ordered Set
The rate match FIFO inserts or deletes only one SKP symbol per SKP ordered set
received. Rate match FIFO insertion and deletion events are communicated to the
FPGA fabric on the pipestatus[2:0] port from each channel. The pipestatus[2:0]
signal is driven to 3'b001 for one clock cycle synchronous to the /K28.5/ COM symbol
of the SKP ordered set in which the /K28.0/ SKP symbol is inserted. The
pipestatus[2:0] signal is driven to 3'b010 for one clock cycle synchronous to the
/K28.5/ COM symbol of the SKP ordered set from which the /K28.0/ SKP symbol is
deleted.
Figure 1–60
SKP symbols are required to be deleted. Only one /K28.0/ SKP symbol is deleted per
SKP ordered set received.
Figure 1–61
symbols are required to be inserted. Only one /K28.0/ SKP symbol is inserted per
SKP ordered set received.
The rate match FIFO full and empty conditions are communicated to the FPGA fabric
on the pipestatus[2:0] port from each channel.
The rate match FIFO in PCIe mode automatically deletes the data byte that causes the
FIFO to go full and drives pipestatus[2:0] = 3'b101 synchronous to the subsequent
data byte.
3'b010
K28.5
First Skip Ordered Set
K28.5
K28.0
K28.0
xxx
shows an example of rate match deletion in the case where two /K28.0/
shows an example of rate match insertion in the case where two SKP
K28.0
K28.0
Dx.y
Dx.y
xxx
xxx
Second Skip Ordered Set
K28.5
Dx.y
xxx
3'b010
K28.5
Dx.y
SKIP Symbol Deleted
3'b001
K28.5
K28.0
Second Skip Ordered Set
SKIP Symbol Inserted
K28.0
K28.5
xxx
K28.0
K28.0
xxx
K28.0
K28.0
xxx
Stratix IV Device Handbook Volume 2: Transceivers
K28.0
K28.0
xxx
K28.0
K28.0
K28.0
K28.0
xxx
xxx
K28.0
xxx
K28.0
K28.0
xxx
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