DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 229

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–4. Number of DQS/DQ Groups per Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA
Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4SE230 and EP4SE360 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011 Altera Corporation
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
(Note
7–4:
1), (2), (3), (4),
32 User I/Os
I/O Bank 2A
32 User I/Os
26 User I/Os
I/O Bank 1A
26 User I/Os
x16/x18=1
I/O Bank 1C
I/O Bank 2C
x16/x18=1
x16/x18=0
x16/x18=0
x8/x9=2
x8/x9=2
x8/x9=1
x8/x9=1
x4=4
DLL1
x4=3
x4=4
x4=3
DLL0
UP
and R
(5)
40 User I/Os
40 User I/Os
I/O Bank 8A
I/O Bank 3A
x16/x18=1
x16/x18=1
DN
x8/x9=3
x8/x9=3
x4=6
x4=6
pins for OCT calibration. If two pins of a ×4 group are used as R
EP4SE230 and EP4SE360 Devices in the
24 User I/Os
I/O Bank 8C
x16/x18=0
I/O Bank 3C
24 User I/Os
x8/x9=1
x16/x18=0
x8/x9=1
x4=2
x4=2
780-Pin FineLine BGA
UP
and R
DN
24 User I/Os
I/O Bank 7C
I/O Bank 4C
24 User I/Os
x16/x18=0
pins, but you cannot use a ×4 group for memory interfaces if two pins
x16/x18=0
x8/x9=1
x8/x9=1
x4=3
x4=3
7–26.
I/O Bank 7A
40 User I/Os
I/O Bank 4A
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
x4=6
x4=6
UP
Stratix IV Device Handbook Volume 1
and R
32 User I/Os
26 User I/Os
32 User I/Os
I/O Bank 6A
26 User I/Os
x16/x18=1
I/O Bank 6C
I/O Bank 5C
x16/x18=0
I/O Bank 5A
x16/x18=1
x16/x18=0
x8/x9=2
x8/x9=1
x8/x9=2
x8/x9=1
x4=4
DN
x4=3
x4=4
x4=3
DLL2
DLL3
pins for OCT calibration, you
“Combining
7–9