DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 572
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 572 of 1154
- Download datasheet (32Mb)
1–128
Stratix IV Device Handbook Volume 2: Transceivers
PCIe Mode Configurations
Stratix IV GX and GT transceivers support both Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
data rates in PCIe functional mode. When configured for the Gen2 (5 Gbps) data rate,
the Stratix IV GX and GT transceivers allow dynamic switching between Gen2
(5 Gbps) and Gen1 (2.5 Gbps) signaling rates. Dynamic switch capability between the
two PCIe signaling rates is critical for speed negotiation during link training.
Stratix IV GX and GT transceivers support ×1, ×4, and ×8 lane configurations in PCIe
functional mode at both 2.5 Gbps and 5 Gbps data rates. In PCIe ×1 configuration, the
PCS and PMA blocks of each channel are clocked and reset independently. PCIe ×4
and ×8 configurations support channel bonding for four-lane and eight-lane PCIe
links. In these bonded channel configurations, the PCS and PMA blocks of all bonded
channels share common clock and reset signals.
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture
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