DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 904

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–58
Figure 5–29. Correct Input Reference Clock Connections When Reusing a .mif
Note to
(1) The red lines represent the alternate source of REFCLK.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
5–29:
1
156.25 MHz
125 MHz
Figure 5–29
You can re-use the .mif generated for a transceiver channel on one side of the device
for a transceiver channel on the other side of the device, only if the input reference
clock frequencies and order of the pll_inclk_rx_cruclk[] ports in the ALTGX
instances on both sides are identical.
In addition to the input reference clock requirements when re-using a .mif, refer to
“Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports” on page 5–58
additional ways to re-use a .mif.
Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports
This section describes when to enable the logical_tx_pll_sel and
logical_tx_pll_sel_en ports and how to use them in the following dynamic
reconfiguration modes:
■
■
■
These are optional input ports to the ALTGX_RECONFIG instance.
Channel and CMU PLL reconfiguration mode
Channel reconfiguration with transmitter PLL select mode
CMU PLL reconfiguration mode
shows the correct input reference clock connections when re-using a .mif.
(1)
(1)
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Stratix IV GX Device
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Transceiver Block 0
Transceiver Block 1
Instance 2
Instance 1
ALTGX
February 2011 Altera Corporation
ALTGX
for