DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 549

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–91. Rateswitch in PCIe Mode
Note to
(1) Time T1 is pending characterization.
February 2011 Altera Corporation
Low-Speed Parallel Clock
Figure
pipephydonestatus
1–91:
rateswitch
1
1
When creating a PCIe Gen2 configuration, configure the CMU PLL to 5 Gbps. This
helps to generate the 2.5 Gbps and 5 Gbps high-speed serial clock using the rateswitch
circuit.
The /S divider receives the clock output from the /N divider or PCIE rateswitch
circuit (only in PCIe mode) and generates the low-speed parallel clock for the PCS
block of all transmitter channels and coreclkout for the FPGA fabric. If the byte
serializer block is enabled in bonded channel modes, the /S divider output is divided
by the /2 divider and sent out as coreclkout to the FPGA fabric. The Quartus II
software automatically selects the /S values based on the deserialization width setting
(single-width or double-width mode) that you select in the ALTGX MegaWizard
Plug-In Manager. For more information about single-width or double-width mode,
refer to
The Quartus II software automatically selects all the divider settings based on the
input clock frequency, data rate, deserialization width, and channel width settings.
“Transceiver Channel Architecture” on page
Low-Speed Parallel Clock Generation
250 MHz (Gen 1)
(Note 1)
T1
500 MHz (Gen 2)
Stratix IV Device Handbook Volume 2: Transceivers
1–17.
T1
250 MHz (Gen 1)
1–105