DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 626

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–182
Figure 1–148. (OIF) CEI PHY Interface Mode Datapath
Figure 1–149. Transceiver Clocking in (OIF) CEI PHY Interface Mode
Stratix IV Device Handbook Volume 2: Transceivers
tx_coreclk
rx_coreclk
FPGA
Fabric
FPGA
Fabric-Transmitter
Interface Clock
FPGA
Fabric-Receiver
Interface Clock
(OIF) CEI PHY Interface Mode Datapath
Figure 1–148
in (OIF) CEI PHY interface mode.
Figure 1–149
Serial RapidIO Mode
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signal, communications, and network processors, system memories, and
peripheral devices.
Serial RapidIO physical layer specification defines three line rates:
■
■
■
Transceiver Block Clocking with the
Use central clock divider to improve
transmitter jitter option disabled
1.25 Gbps
2.5 Gbps
3.125 Gbps
rx_clkout
CMU PLL
Compensation
Compensation
tx_clkout
wrclk
RX Phase
TX Phase
FIFO
FIFO
shows the ALTGX megafunction transceiver datapath when configured
shows transceiver clocking in (OIF) CEI PHY interface mode.
rdclk
Local Clock Divider Block
Local Clock Divider Block
Local Clock Divider Block
Local Clock Divider Block
wrclk
Serializer
/2
Byte
Ch 3
Ch 2
Ch 1
Ch 0
rdclk
Serializer
Parallel Recovered Clock
Byte
Low-Speed Parallel Clock
De-
Transmitter Channel PCS
/2
Receiver Channel PCS
Chapter 1: Transceiver Architecture in Stratix IV Devices
Channel 3
Channel 2
Channel 1
Channel 0
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Serializer
Divider
Clock
Local
February 2011 Altera Corporation
CDR
High-Speed Serial Clock
Transceiver Block Architecture