DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 210
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
6–38
Figure 6–26. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
Notes to
(1) ts2p ≥ 25 ns.
(2) S2PENA_1A is asserted in Bank 1A for calibration block 0.
(3) S2PENA_2A is asserted in Bank 2A for calibration block 1.
Termination Schemes for I/O Standards
Stratix IV Device Handbook Volume 1
Figure
Single-Ended I/O Standards Termination
S2PENA_1A (2)
S2PENA_2A (3)
OCTUSRCLK
6–26:
ENASER0
ENASER1
nCLRUSR
1
ENAOCT
Example of Using Multiple OCT Calibration Blocks
Figure 6–26
and R
asserting the ENASER signals at different times. ENAOCT must remain asserted while any
calibration is ongoing. You must set nCLRUSR low for one OCTUSRCLK cycle before each
ENASER[N] signal is asserted. In
time to initialize OCT calibration block 0, this does not affect OCT calibration block 1,
whose calibration is already in progress.
R
If only R
signal only requires to be asserted for 240 OCTUSRCLK cycles.
You must assert the ENASER signal for 28 OCTUSRCLK cycles for serial transfer.
The following sections describe the different termination schemes for the I/O
standards used in Stratix IV devices.
Voltage-referenced I/O standards require both an input reference voltage, V
termination voltage, V
termination voltage of the transmitting device.
Figure 6–27
Stratix IV devices.
S
Calibration
T
calibration. Calibration blocks can start calibrating at different times by
S
calibration is used for an OCT calibration block, its corresponding ENASER
shows a signal timing waveform for two OCT calibration blocks doing R
and
1000
CY CLE S
OCTUSRCLK
Figure 6–28
Calibration Phase
1000
TT
CY CLE S
. The reference voltage of the receiving device tracks the
OCTUSRCLK
show the details of SSTL and HSTL I/O termination on
Figure
6–26, when you set nCLRUSR to 0 for the second
28
OCTUSRCLK
CY CLE S
Chapter 6: I/O Features in Stratix IV Devices
ts2p (1)
28
Termination Schemes for I/O Standards
OCTUSRCLK
CY CLE S
February 2011 Altera Corporation
ts2p (1)
REF
, and a
S
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