DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 935
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 935 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Duration
Dynamic Reconfiguration Duration
February 2011 Altera Corporation
■
Dynamic reconfiguration duration is the number of cycles the busy signal is asserted
when the dynamic reconfiguration controller performs write transactions, read
transactions, or offset cancellation of the receiver channels.
PMA Controls Reconfiguration Duration
The following section contains an estimate of the number of reconfig_clk clock
cycles the busy signal is asserted during PMA controls reconfiguration using
Method 1, Method 2, or Method 3. For more information, refer to
Reconfiguring PMA Controls” on page 5–13
■
■
■
■
■
Enable self recovery option—When you select this option, the controller
automatically recovers if the operation did not complete within the expected time.
The error signal is driven high whenever the controller performs a self recovery.
TX Data Rate Switch using Local Divider-write operation without input port
option:
TX Data Rate Switch using Local Divider- read operation without output
port option:
Channel and/or TX PLL reconfig/select-read operation option:
Adaptive Equalization option—read operation:
EyeQ option—read operation:
■
■
■
■
■
■
■
■
■
■
■
■
The rate_switch_ctrl input port is not used
The reconfig_mode_sel port is set to 3 (if other reconfiguration mode
options are selected in the Reconfiguration settings screen)
The write_all signal is asserted
The rate_switch_out output port is not used
The reconfig_mode_sel port is set to 3 (if other reconfiguration mode
options are selected in the Reconfiguration settings screen)
The read signal is asserted
The reconfig_mode_sel input port is set to 4, 5, 6, or 7
The read signal is asserted
The reconfig_mode_sel input port is set to 7, 8, 9, or 10
The read signal is asserted
The reconfig_mode_sel input port is set to 11
The read signal is asserted
.
Stratix IV Device Handbook Volume 2: Transceivers
“Dynamically
5–89
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