DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 709

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–22. Transmitter Channel Clocking for 17 Channels Configured in Basic (PMA Direct) ×N Mode
February 2011 Altera Corporation
Fabric
FPGA
1
CMU0_PLL
Figure 2–22
(PMA Direct) ×N mode.
Figure 2–22
located across three transceiver blocks on the right side of the Stratix IV device. Each
of the two transceiver blocks, GXBR0 and GXBR2, contain six of the 17 ×N bonded
channels located in four regular channels and two CMU channels. The remaining five
of the 17 ×N bonded channels are located in four regular channels and the CMU1
channel of the transceiver block GXBR1.
Stratix IV devices allow both CMU channels and 6G ATX PLL blocks to generate the
high-speed serial and low-speed parallel transceiver clocks when configured in Basic
(PMA Direct) ×N mode.
shows transmitter channel clocking for 17 channels configured in Basic
shows 17 channels configured in Basic (PMA Direct) ×N mode and
Divider
CMU0
Clock
CMU1_Channel
Regular Channel TX PCS
Regular Channel TX PCS
Regular Channel TX PCS
Transmitter Channel PMA
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
Regular Channel TX PMA
Regular Channel TX PMA
CMU0 Channel TX PMA
Regular Channel TX PMA
CMU1 Channel TX PMA
CMU0 Channel TX PMA
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
Stratix IV Device Handbook Volume 2: Transceivers
Low-Speed Parallel clock
Low-Speed Parallel clock
Low-Speed Parallel clock
High-Speed Serial and
High-Speed Serial and
High-Speed Serial and
xN_Bottom
xN_Top
x4
2–37