DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 650

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–206
Built-In Self Test Modes
Figure 1–173. Input and Output Ports for BIST Modes
Notes to
(1) rx_serilalpbken is required in PRBS.
(2) rx_bisterr and rx_bistdone are only available in PRBS and BIST modes.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
BIST Mode Pattern Generators and Verifiers
1–173:
rx_seriallpbken[] (1)
This section describes Built-In Self Test (BIST) modes.
Each transceiver channel in the Stratix IV GX and GT devices contain a different BIST
pattern generator and verifier. Using these BIST patterns, you can verify the
functionality of the functional blocks in the transceiver channel without requiring
user logic. The BIST functionality is provided as an optional mechanism for
debugging transceiver channels.
ports when you select BIST mode (except incremental patterns).
Three types of pattern generators and verifiers are available:
■
■
■
rx_digitalreset
tx_digitalreset
BIST incremental data generator and verifier—This is only available in parallel
loopback mode. For more information, refer to
High frequency and low frequency pattern generator—The high frequency
patterns generate alternate ones and zeros and the low frequency patterns
generate five ones and five zeroes in single-width mode and ten ones and ten
zeroes in double-width mode. These patterns do not have a corresponding verifier.
You can enable the serial loopback option to dynamically loop the generated
pattern to the receiver channel using the rx_seriallpbken port. Therefore, the
8B/10B encoder/decoder blocks are bypassed in the Basic PRBS mode.
Pseudo Random Binary Sequence (PRBS) generator and verifier—The PRBS
generator and verifier interface with the serializer and deserializer in the PMA
blocks. The advantage of using a PRBS data stream is that the randomness yields
an environment that stresses the transmission medium. In the data stream, you
can observe both random jitter and deterministic jitter using a time interval
analyzer, bit error rate tester, or oscilloscope. The PRBS repeats after completing an
iteration. The number of bits the PRBSx pattern sends before repeating the pattern
is (2
tx_datain[]
pll_inclk
^x -1
) bits.
Built-In Self Test
(BIST)
Figure 1–173
Chapter 1: Transceiver Architecture in Stratix IV Devices
shows the enabled input and output
tx_dataout
rx_bisterr (2)
rx_bistdone (2)
“Serial Loopback” on page
February 2011 Altera Corporation
Built-In Self Test Modes
1–190.