DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 507
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
The following functional modes support the 10-bit PMA-PCS interface:
■
■
■
■
■
■
This section describes the following word aligner 10-bit PMA-PCS interface modes:
■
■
■
Table 1–27
10-bit PMA-PCS interface.
Table 1–27. Word Aligner Configurations with a 10-Bit PMA-PCS Interface
Protocols such as PCIe, XAUI, Gigabit Ethernet, and Serial RapidIO require the
receiver PCS logic to implement a synchronization state machine to provide hysteresis
during link synchronization. Each of these protocols defines a specific number of
synchronization code groups that the link must receive to acquire synchronization
and a specific number of erroneous code groups that it must receive to fall out of
synchronization.
In PCIe, XAUI, Gigabit Ethernet, and Serial RapidIO functional modes, the Quartus II
software configures the word aligner in automatic synchronization state machine
mode. It automatically selects the word alignment pattern length and pattern as
specified by each protocol. In each of these functional modes, the protocol-compliant
synchronization state machine is implemented in the word aligner.
PCIe
Serial RapidIO
XAUI
GIGE
SDI
Basic single-width
mode
PCIe Gen1 and Gen2
Serial RapidIO
XAUI
GIGE
SDI
Basic single-width mode
Automatic synchronization state machine mode with 10-bit PMA-PCS interface
mode
Manual alignment mode with 10-bit PMA-PCS interface mode
Bit-slip mode with 10-bit PMA-PCS interface mode
Functional Mode
Word Aligner in Single-Width Mode with 10-Bit PMA-PCS Interface Modes
Automatic Synchronization State Machine Mode Word Aligner with 10-Bit PMA-PCS
Interface Mode
lists the word aligner configurations allowed in functional modes with a
Automatic synchronization state machine
Automatic synchronization state machine
Automatic synchronization state machine
Automatic synchronization state machine
Bit-slip
Manual alignment, Automatic
synchronization state machine, Bit-slip
Allowed Word Aligner Configurations
Stratix IV Device Handbook Volume 2: Transceivers
Allowed Word Alignment
Pattern Length
7 bits, 10 bits
7 bits, 10 bits
7 bits, 10 bits
10 bits
10 bits
N/A
1–63
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