DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 831

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: Reset Control and Power Down in Stratix IV Devices
PMA Direct Drive Mode Reset Sequences
Figure 4–13. Reset Sequence Timing in Basic (PMA Direct) Drive ×4 Mode
Note to
(1) For t
February 2011 Altera Corporation
Figure
pll_powerdown
Reset and Power-Down Signals
Ouput Status Signals
Basic (PMA Direct) Drive ×N Mode
4–13:
pll_powerdown
duration, refer to the
pll_locked
When bonding ×N channels in a Basic (PMA Direct) drive mode configuration, you
can reset all bonded channels simultaneously.
Transmitter Only Channel with No PLL_L/R
Figure 4–13
Only channels in Basic (PMA Direct) drive ×4 functional mode with no PLL_L/R.
As shown in
drive functional ×4 mode with no PLL_L/R, follow these reset steps:
1. After power up, assert pll_powerdown for a minimum of t
2. When the transmitter PLL locks, as indicated by the pll_locked signal going high
between markers 1 and 2).
(marker 3), the transmitter is ready to accept parallel data from the FPGA fabric
and subsequently transmitting serial data reliably.
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
shows an example reset sequence timing diagram of four Transmitter
Figure
2
4–13, for the Transmitter Only channel in Basic (PMA Direct)
3
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
pll_powerdown
(the time
4–25