DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 678
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 678 of 1154
- Download datasheet (32Mb)
2–6
Figure 2–4. Input Reference Clock Sources Across Transceiver Blocks for Stratix IV GT Devices
Stratix IV Device Handbook Volume 2: Transceivers
To FPGA Fabric
Figure 2–4
receiver CDRs in four transceiver blocks on the right side of the EP4S100G5F45
device. In this figure, the input reference clock sources for four transceiver blocks are
located only on the right side of the EP4S100G5F45 device but the device has similar
input reference clock resources available for the four transceiver blocks located on the
left side of the device as well.
Figure 2–4
device. The number of ITB clock lines available in any Stratix IV GT device is equal to
the number of refclk pins available in that device.
shows the input reference clock sources for CMU PLLs, ATX PLLs, and
also shows the ITB clock lines on the right side of the EP4S100G5F45
ITB[7:0]
8
refclk0
refclk0
refclk1
refclk0
refclk0
refclk1
6
6
refclk1
6
refclk1
6
2
2
2
2
2
2
2
2
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
Global Clock Line
PLL Cascade Clock
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
Chapter 2: Transceiver Clocking in Stratix IV Devices
8
8
6
6
6
8
6
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
ATX PLL R2 (10G)
ATX PLL R1 (6G)
ATX PLL R0 (6G)
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Four RX CDRs
Four RX CDRs
Four RX CDRs
Four RX CDRs
February 2011 Altera Corporation
and
and
and
and
Input Reference Clocking
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