DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 521
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 521 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–59. Deskew FIFO Operation in XAUI Functional Mode
Note to
(1) This figure is from IEEE P802.3ae.
February 2011 Altera Corporation
Figure
1–59:
The deskew operation in XAUI functional mode is compliant to the PCS deskew state
machine diagram specified in clause 48 of IEEE P802.3ae, as shown in
Rate Match (Clock Rate Compensation) FIFO
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clocks. Frequency differences in the order of a few
hundred PPM can corrupt the data when latching from the recovered clock domain
(the same clock domain as the upstream transmitter reference clock) to the local
receiver reference clock domain.
The rate match FIFO compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing SKP
symbols or ordered sets from the IPG or idle streams. It deletes SKP symbols or
ordered sets when the upstream transmitter reference clock frequency is higher than
the local receiver reference clock frequency. It inserts SKP symbols or ordered-sets
when the local receiver reference clock frequency is higher than the upstream
transmitter reference clock frequency.
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
SUDI(![/||A||/])
enable_deskew
enable_deskew
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
LOSS_OF_ALIGNMENT
enable_deskew
1
2
3
ALIGN_ACQUIRED_1
ALIGN_ACQUIRED_2
ALIGN_ACQUIRED_3
ALIGN_ACQUIRED_4
align_status
ALIGN_DETECT_1
ALIGN_DETECT_2
ALIGN_DETECT_3
(Note 1)
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
sync_status OK * SUDI(![/||A||/])
⇐
⇐
⇐
⇐
FAIL
FALSE
FALSE
TRUE
1
2
3
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
reset +
(sync_status=FAIL * SUDI)
Stratix IV Device Handbook Volume 2: Transceivers
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
Figure
1–59.
1–77
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: