DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 636

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–192
Figure 1–156. Enabled PCS Functional Blocks in Parallel Loopback
Table 1–69. Enabled PCS Functional Blocks for Parallel Loopback
Stratix IV Device Handbook Volume 2: Transceivers
Configuration
Single-width mode
Double-width mode
FPGA
Fabric
BIST incremental
pattern generator
BIST incremental
Compen-
pattern verifier
sation
FIFO
RX
The parallel loopback mode is available only with a built-in 16-bit incremental pattern
generator and verifier. The channel width is fixed to 16 bits in this mode. Also in this
mode, the incremental pattern 00-FF is looped back to the receiver channel at the PCS
functional block boundary before the PMA and is sent to the tx_dataout port. The
received data is verified by the verifier. This loopback allows you to verify the
complete PCS block. The differential output voltage of the transmitted serial data on
the tx_dataout port is based on the selected V
loopback is shown in
the FPGA logic for verification.
Table 1–69
mode. The last column in
parallel loopback.
The status signals rx_bistdone and rx_bisterr indicate the status of the verifier. The
rx_bistdone port is asserted and stays high when the verifier either receives one full
cycle of incremental pattern or it detects an error in the receiver data. The rx_bisterr
signal is asserted and stays high when the verifier detects an error. You can reset the
incremental pattern generator and verifier by asserting the tx_digitalreset and
rx_digitalreset signals, respectively.
8B/10B Encoder
Compen-
Phase
sation
FIFO
TX
Enabled
Enabled
lists the enabled PCS functional blocks for single-width and double-width
Serializer
Byte
serializer
Byte
De-
Byte Serializer
Figure
Disabled
Enabled
Table 1–69
Encoder
8B/10B
1–156. The incremental data pattern is not available to
Decoder
Receiver Channel PCS
8B/10B
600 Mbps to 3.125 Gbps
Transmitter Channel PCS
lists the supported channel width setting for
Data Rate Range
1 Gbps to 5 Gbps
Chapter 1: Transceiver Architecture in Stratix IV Devices
Aligner
Word
OD
settings. The datapath for parallel
loopback
Parallel
MegaWizard Plug-In Manager
February 2011 Altera Corporation
Supported Channel Width
serializer
Serializer
Transmitter Channel PMA
for Parallel Loopback
Receiver Channel PMA
De-
Setting in the ALTGX
Transceiver Block Architecture
Receiver
CDR
16
16