DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 551

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–93. Functional Blocks Enabled to Support Transceiver Channel Functionality
Table 1–39. Transmit and Receive Serial Pins (Part 1 of 2)
February 2011 Altera Corporation
tx_data_out
rx_data_in
REFCLK_[L,R][0,2,4,6]P,
GXB_CMURX_[L_R][0,2,4,6]P
GXB_TX_[L,R][0,2,4,6]
REFCLK_[L,R][1,3,5,7]P,
GXB_CMURX_[L_R][1,3,5,7]P
CMU Channel
1
Pins
High-speed clock
from the adjacent
Figure 1–93
channel functionality.
The CMU PLL is configured as a CDR to recover data. The dedicated input reference
clock pin is configured to receive serial data.
When configured as a full-duplex or receiver-only channel, the CMU PLL performs
the functionality of the receiver CDR and recovers clock from the incoming serial
data. The high-speed serial and low-speed parallel recovered clocks are used by the
deserializer in the CMU channel and the deserialized data is forwarded directly to the
FPGA fabric.
When configured as a full-duplex or transmitter-only channel, the serializer in the
CMU channel serializes the parallel data from the FPGA fabric and drives the serial
data to the transmitter buffer.
Table 1–39
CMU channel
(1)
(2)
(3)
(2)
CONFIGURED AS
lists the pins that are used as transmit and receive serial pins.
shows the functional blocks that are enabled to support the transceiver
CMU PLL
RX CDR
divider block
CMU Clock
(/1, /2, /4)
x4 clock line
Receive serial input for CMU Channel0
Receive serial input for CMU Channel1
When a CMU Channel is Configured
Transmit serial output for CMU
as a Transceiver Channel
Channel0
clock line
From xN
serializer
deserializer
top
Stratix IV Device Handbook Volume 2: Transceivers
clock line
From xN
bottom
When a CMU Channel is
Input reference clocks
Input reference clocks
Configured for Clock
Not available for use
From the
FPGA
Generation
fabric
FPGA
1–107
To the
fabric