DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 202

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

6–30
Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices
Stratix IV Device Handbook Volume 1
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f
1
50 Ω
50
Transmitter
50 Ω
Stratix IV OCT
When using calibrated input parallel and calibrated output series termination on
bidirectional pins, they must use the same termination value because each I/O pin
can only reference one OCT calibration block. The only exception is when using 50 Ω
parallel OCT and 25 Ω series OCT using the left shift series termination control. For
example, you cannot use calibrated 50 Ω parallel OCT on the input buffer of a
bidirectional pin and calibrated 40 Ω series OCT on the output buffer because these
would require two separate calibration blocks with different RUP and RDN resistor
values.
For more information about tolerance specifications for OCT with calibration, refer to
the
Stratix IV OCT
DC and Switching Characteristics for Stratix IV Devices
VCCIO
VCCIO
GND
GND
100 Ω
100 Ω
100 Ω
100
100 Ω
100
Z
Z
O
O
= 50 Ω
= 50 Ω
On-Chip Termination Support and I/O Termination Schemes
100 Ω
100 Ω
100 Ω
100 Ω
100 Ω
100
100 Ω
100
VCCIO
VCCIO
GND
GND
Stratix IV OCT
Stratix IV OCT
Chapter 6: I/O Features in Stratix IV Devices
chapter.
Transmitter
February 2011 Altera Corporation
Receiver
50 Ω
50 Ω
50