DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 614
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 614 of 1154
- Download datasheet (32Mb)
1–170
Figure 1–136. Synchronization State Machine in GIGE Mode
Note to
(1) This figure is from IEEE P802.3ae.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
1–136:
Table 1–64
GIGE mode.
Table 1–64. Synchronization State Machine Parameters in GIGE Functional Mode
Figure 1–136
Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve synchronization
Number of errors received to lose synchronization
Number of continuous good code groups received to reduce the error count by 1
2
3
lists the synchronization state machine parameters when configured in
shows the synchronization state machine implemented in GIGE mode.
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
SYNC_ACQUIRED_2
SYNC_ACQUIRED_3
SYNC_ACQUIRED_4
cgbad
cgbad
cgbad
[PUDI * signal_detect=FAIL +
mr_loopback=FALSE] +
PUDI(![/COMMA/])
Synchronization State Machine Parameters
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
0
0
0
PUDI(![/|DV|/]
cgbad
PUDI(![/|DV|/]
cgbad
PUDI(![/|DV|/]
cggood
cggood
cggood
SUDI
SUDI
SUDI
SUDI
SUDI
SUDI
COMMA_DETECT_1
COMMA_DETECT_2
rx_even
COMMA_DETECT_3
sync_status
rx_even
rx_even
ACQUIRE_SYNC_1
ACQUIRE_SYNC_2
LOSS_OF_SYNC
rx_even
rx_even
rx_even
cgbad
cgbad
cgbad
cgbad
(Note 1)
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
PUDI([/|DV|/]
(signal_detect=OK+mr_loopback=TRUE)* *
PUDI([/COMMA/]
rx_even=FALSE+PUDI([/COMMA/]
PUDI([/|DV|/]
rx_even=FALSE+PUDI([/COMMA/]
TRUE
TRUE
TRUE
⇐
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
SYNC_ACQUIRED_2A
SYNC_ACQUIRED_3A
SYNC_ACQUIRED_4A
FAIL
PUDI([/|DV|/]
power_on=TRUE+mr_main_rest=TRUE +
(signal_detectCHANGE=TRUE +
mr_loopback=FALSE +PUDI)
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
2
3
good_cgs + 1
good_cgs + 1
good_cgs + 1
Chapter 1: Transceiver Architecture in Stratix IV Devices
cggood
cggood
PUDI(![/COMMA/]
*∉[/INVALID/]
PUDI(![/COMMA/]
*∉[/INVALID/]
SUDI
SYNC_ACQUIRED_1
*good_cgs = 3
*good_cgs = 3
rx_even
sync_status
⇐
cggood
cggood
cggood
! rx_even
⇐
cggood
OK
*good_cgs = 3
*good_cgs = 3
*good_cgs = 3
*good_cgs = 3
cggood
February 2011 Altera Corporation
Transceiver Block Architecture
Setting
3
4
4
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: