DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 557

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–94. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit PMA-PCS Interface for Stratix IV GX
Devices
Note to
(1) The maximum data rate specification shown in
February 2011 Altera Corporation
other speed grades offered, refer to the
Figure
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
(1)
(1)
TX PCS Latency
Interface Frequency
RX PCS Latency
1–94:
Interface Frequency
Interface Frequency
Fabric-Transceiver
Fabric-Transceiver
Low-Latency PCS
Rate Match FIFO
Data Rate (Gbps)
Encoder/Decoder
Data Rate (Gbps)
Channel Bonding
Interface Width
(Pattern Length)
Interface Width
FPGA Fabric -
FPGA Fabric
Byte Ordering
Byte SerDes
Word Aligner
Transceiver
Transceiver
Interface Width
PMA-PCS
Functional
FPGA
(MHz)
PMA-PCS
8B/10B
FPGA
Modes
Basic Single-Width Mode Configurations
Figure 1–94
single-width functional mode with an 8-bit PMA-PCS interface.
Figure 1–95
single-width functional mode with an 8-bit PMA-PCS interface.
8-bit
Disabled
Disabled
Single
Width
11-13
8-Bit
0.6 -
75 -
5 -6
DC and Switching Characteristics
2.0
250
shows Stratix IV GX transceiver configurations allowed in Basic
shows Stratix IV GT transceiver configurations allowed in Basic
Manual Alignment
10-Bit
Disabled
Disabled
(16-Bit)
Basic
Figure 1–94
195.3125
Disabled
4 - 5.5
16-Bit
16-Bit
37.5 -
7 - 9
Enabled
Double
Width
3.125
0.6 -
Disabled
195.3125
20-Bit
Enabled
16-Bit
4 - 5.5
37.5 -
Stratix IV GX Configurations
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
7 - 9
10-Bit
PIPE
Disabled
Disabled
11 - 13
8-Bit
0.6 -
75 -
5 -6
2.0
250
chapter.
Disabled
Disabled
Bit-Slip
(16-Bit)
10-Bit
XAUI
Basic Single-Width
8-Bit PMA-PCS
Interface Width
195.3125
Enabled
Disabled
x1, x4, x8
4 - 5.5
16-Bit
0.6 - 3.2
37.5 -
3.125
0.6 -
7 - 9
GIGE
10-Bit
Protocol
SRIO
10-Bit
Stratix IV Device Handbook Volume 2: Transceivers
SONET
/SDH
8-Bit
16-Bit
(OIF)
CEI
10-Bit
SDI
Disabled
Disabled
8-Bit
0.6 -
4 - 5
3 - 4
75 -
250
2.0
Disabled
Disabled
Disabled
Enabled
10
Deterministic
-Bit
Latency
Disabled
Enabled
16-Bit
37.5 -
4 - 5.5
3 - 4.5
200
0.6 -
3.2
20-Bit
1–113