DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 595

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
1
Fundamental reset is provided by the system to the component or adapter card using
the auxiliary signal PERST#. The PCIe Base Specification 2.0 specifies that PERST# must
be kept asserted for a minimum of 100 ms (TPVPERL) after the system power becomes
stable in a cold reset situation. Additionally, all system components must enter the
LTSSM Detect state within 20 ms and the link must become active within 100 ms after
de-assertion of the PERST# signal. This implies that each PCIe system component must
become active within 200 ms after the power becomes stable.
The link being active is interpreted as the physical layer device coming out of
electrical idle in the L0 state of the LTSSM state machine.
Figure 1–120
Figure 1–120. PCIe Cold Reset Requirements
The time taken by a PCIe port implemented using the Stratix IV GX and GT device to
go from power up to link active state is described below:
■
■
■
To meet the PCIe specification of 200 ms from power on to link active, the
Stratix IV GX and GT device configuration time must be less than 148 ms
(200 ms –12 ms for power on reset and -40 ms for the link to become active after
PERST# de-assertion).
Power on reset (POR)—begins after power rails become stable. Typically takes
12 ms
FPGA configuration/programming—begins after POR. Configuration time
depends on the FPGA density
Time taken from de-assertion of PERST# to link active—typically takes 40 ms
(pending characterization and verification of PCIe soft IP and hard IP)
Power Rail
PERST#
lists the PCIe cold reset timing requirements.
1
T
PVPERL
100 ms
2
d" 20 ms
T
2-3
d" 100 ms
T
3
2-4
4
Stratix IV Device Handbook Volume 2: Transceivers
Marker 1: Power becomes stable
Marker 2: PERST# gets de-asserted
Marker 3: Maximum time for Marker 2 for
the LTSSM to enter the Detect state
Marker 4: Maximum time for Marker 2 for
the link to become active
1–151