DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 310
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
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8–32
Figure 8–26. Bit-Order and Word Boundary for One Differential Channel
Note to
(1) These are only functional waveforms and are not intended to convey timing information.
Stratix IV Device Handbook Volume 1
Transmitter Channel
Operation (x8 Mode)
Operation (x8 Mode)
Receiver Channel
rx_out [7..0]
tx_outclock
rx_outclock
rx_inclock
Figure
tx_out
rx_in
8–26:
X
7
X X X X X X X
6
X X X X X X X X
For other serialization factors, use the Quartus II software tools to find the bit position
within the word.
Table 8–11
The MSB and LSB positions increase with the number of channels used in a system.
Table 8–11. Differential Bit Naming
5
Receiver Channel Data Number
Previous Cycle
4
3
2
lists the conventions for differential bit naming for 18 differential channels.
1
0
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
MSB
7
X
Table 8–11
6
X
Current Cycle
5
X X X X X X X X
X
4 3
X
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
X
2
lists the bit positions after deserialization.
X
1
LSB
X
0
X X X
X
Next Cycle
MSB Position
X
X
103
111
119
127
135
143
15
23
31
39
47
55
63
71
79
87
95
X X X X 7 6 5 4
(Note 1)
7
X X X X X
X
Internal 8-Bit Parallel Data
X
X
X
X
X
Source-Synchronous Timing Budget
February 2011 Altera Corporation
X
X
X
LSB Position
3 2 1 0 X X X X
X
104
112
120
128
136
16
24
32
40
48
56
64
72
80
88
96
0
8
X
X
X
X
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