DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 907
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 907 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–31. Input Reference Clocks Connections to the Transceiver Channels
Note to
(1) Depending on the mode you select, the PCS unit may or may not be present.
February 2011 Altera Corporation
Figure
5–31:
(Identification
number = 2)
(Identification
number = 1)
Refclk0
Refclk1
156 .25 MHz
125MHz
Figure 5–31
to the transceiver channels are based on what you set as the input clock source for
each of the CMU transmitter PLLs within a transceiver block.
Based on what you have set up
selects the corresponding input
as the input clock source for
clock source for CMU0 PLL.
CMU0 PLL, this clock mux
shows an example scenario where the input reference clock connections
Based on what you have set up
selects the corresponding input
as the input clock source for
clock source for CMU1 PLL.
CMU1 PLL, this clock mux
clock
mux
clock
mux
CMU Channels
CMU0 PLL
CMU1 PLL
3.125 Gbps
1 Gbps
TX PLL
Logical
select
TX PLL
clock
Logical
mux
select
clock
mux
Full Duplex Transceiver Channel 1
Full Duplex Transceiver Channel 2
Stratix IV Device Handbook Volume 2: Transceivers
DIVIDER
TX CHANNEL 1
RX CHANNEL 1
LOCAL
3.125 Gbps
DIVIDER
RX CHANNEL 2
RX CDR
TX CHANNEL 2
LOCAL
RX CDR
1 Gbps
TX PMA + TX PCS
RX PMA + RX PCS
TX PMA + TX PCS
RX PMA + RX PCS
3.125 Gbps
3.125 Gbps
1 Gbps
1 Gbps
(1)
(1)
5–61
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