DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 458

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–14
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–9
the EP4S100G3F45 and EP4S100G4F45 Stratix IV GT devices.
Figure 1–9. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S100G3F45 and
EP4S100G4F45 Stratix IV GT Devices
Note to
(1) EP4S100G2F40C2ES1 devices do not have 10G ATX PLL blocks. Use the CMU PLL to generate transceiver clocks for
channels configured at 11.3 Gbps.
Figure
EP4S100G3F45, EP4S100G4F45
shows the transceiver channel, PLL, and PCIe hard IP block locations for
1–9:
Transceiver Block QL0
Transceiver Block QL0
Transceiver Block QL2
Transceiver Block QL1
CMU Channel 1
CMU Channel 0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
Channel 3 (8G)
Channel 2 (8G)
Channel 1 (8G)
Channel 0 (8G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
CMU Channel 1
CMU Channel 0
ATX PLL (10G)
ATX PLL (6G)
ATX PLL (6G)
(Note 1)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block QR0
Transceiver Block QR2
Transceiver Block QR1
Transceiver Block QR0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
ATX PLL (10G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
CMU Channel 1
CMU Channel 0
ATX PLL (6G)
CMU Channel 1
CMU Channel 0
Channel 3 (8G)
Channel 2 (8G)
Channel 1 (8G)
Channel 0 (8G)
ATX PLL (6G)
February 2011 Altera Corporation
Transceiver Channel Locations